| 2.5D Integration | 2.5D 整合 |
| 3D IC Integration | 3D IC整合 |
| 3D Integrated RF Filters | 3D 集成射頻濾波器 |
| 3D Stacking | 3D 疊層技術 |
| 3D TSV Integration | 3D 矽穿孔整合 |
| 5G mmWave Packaging | 5G 毫米波封裝 |
| Acoustic Emission | 聲發射 |
| Active Device | 主動裝置 |
| Active Load | 主動負載 |
| Active Thermal Management | 主動式熱管理 |
| Adaptive Control | 自適應控制 |
| Adaptive Thermal Management | 自適應熱管理 |
| Adaptive Voltage Scaling | 自適應電壓調整 |
| Adaptive Voltage Scaling (AVS) | 自適應電壓調整 |
| Advanced Flip Chip Bumping | 高階覆晶凸點技術 |
| Advanced Silicon Substrate | 高階矽基板 |
| Advanced Substrate Technology | 先進基板技術 |
| Aging Factor | 老化因子 |
| Aging Test | 老化測試 |
| Air Gap Dielectric | 氣隙介電層 |
| Air Gap Thermal Insulation | 氣隙熱絕緣 |
| Amplifier Gain | 放大器增益 |
| Analog Front-End (AFE) | 類比前端 |
| Analog-to-Digital Converter (ADC) | 類比數位轉換器 |
| Anisotropic Conductive Film (ACF) | 異方性導電膜 |
| Annealing | 退火 |
| Assembly | 組裝 |
| Assembly Line Yield | 組裝線良率 |
| Atomic Layer Deposition (ALD) | 原子層沉積 |
| Automated Test Equipment (ATE) | 自動測試設備 |
| Back Grinding | 背面研磨 |
| Backend of Line (BEOL) | 後段製程 |
| Backend Process | 後端製程 |
| Backside Illumination (BSI) | 背照式 |
| Backside Metallization | 背面金屬化 |
| Backside Wafer Processing | 晶圓背面處理 |
| Ball Bond | 球鍵合 |
| Ball Bonding | 球接合 |
| Ball Grid Array (BGA) | 球柵陣列封裝 |
| Bandwidth | 頻寬 |
| Bias Temperature Instability (BTI) | 偏壓溫度不穩定性 |
| BiCMOS | 雙極性互補金氧半導體 |
| Bipolar Transistor | 雙極電晶體 |
| Bonded Interconnect | 鍵合互連 |
| Built-In Self-Test (BIST) | 自建測試 |
| Built-in Thermal Sensing | 內建熱感測 |
| Bump Metallization | 凸點金屬化 |
| Burn-In Board (BIB) | 老化測試板 |
| Burn-in Reliability Test | 老化可靠性測試 |
| Burn-in Test | 老化測試 |
| Capacitance Density | 電容密度 |
| Capacitive Coupling | 電容耦合 |
| Capillary Underfill | 毛細填充膠 |
| Cavity Package | 腔體封裝 |
| Characterization | 特性分析 |
| Charge Pump | 電荷幫浦 |
| Charge Storage | 電荷儲存 |
| Charge-Coupled Device (CCD) | 電荷耦合元件 |
| Chemical Mechanical Polishing (CMP) | 化學機械研磨 |
| Chemical Vapor Deposition (CVD) | 化學氣相沉積 |
| Chip Alignment Tolerance | 晶片對準容差 |
| Chip Interconnection | 晶片互連 |
| Chip on Film (COF) | 晶片對薄膜封裝 |
| Chip on Glass (COG) | 晶片對玻璃封裝 |
| Chip Package System (CPS) | 晶片封裝系統 |
| Chip Scale Package (CSP) | 晶片尺寸封裝 |
| Chip Stacking Density | 晶片堆疊密度 |
| Chip-First Integration | 晶片先整合 |
| Chip-Last Integration | 晶片後整合 |
| Chiplet | 小晶片 |
| Chiplet-Based Architecture | 晶片組架構 |
| Chip-on-Film Integration | 晶片對薄膜整合 |
| Chip-On-Substrate (CoS) | 晶片對基板封裝 |
| Chip-on-Wafer (CoW) | 晶片對晶圓封裝 |
| Chip-on-Wafer-on-Substrate (CoWoS) | 晶片對晶圓對基板封裝 |
| Chip-Package Co-Design | 晶片封裝協同設計 |
| Chip-Package Interaction (CPI) | 晶片封裝互動 |
| Chip-to-Wafer Bonding | 晶片對晶圓鍵合 |
| Clean Process | 清洗製程 |
| Cleanroom | 無塵室 |
| Clock Skew | 時鐘偏移 |
| Clock Tree Synthesis (CTS) | 時鐘樹綜合 |
| CMOS (Complementary Metal-Oxide-Semiconductor) | 互補金氧半導體 |
| CMP (Chemical Mechanical Planarization) | 化學機械平坦化 |
| CMP Slurry | 化學機械研磨漿料 |
| Cold Solder Joint | 冷焊點 |
| Compact Module Integration | 緊湊模組整合 |
| Compression Molded Underfill | 壓模填充膠 |
| Compression Molding | 壓模成型 |
| Conductive Particle Interconnect | 導電粒子互連 |
| Conductor Thickness Uniformity | 導體厚度均勻性 |
| Conformal Coating | 共形塗層 |
| Conformal Encapsulation | 共形封裝 |
| Conformal Shielding | 共形屏蔽 |
| Contact Resistance | 接觸電阻 |
| Contact Resistance Measurement | 接觸電阻測量 |
| Control Logic | 控制邏輯 |
| Controlled Collapse Chip Connection (C4) | 可控塌陷晶片連接 |
| Copper Interconnect | 銅互連 |
| Copper Pillar Microbumping | 銅柱微凸點 |
| Critical Dimension (CD) | 臨界尺寸 |
| Cross-Layer Interconnect | 跨層互連 |
| Cross-Talk | 串音 |
| Cu Pillar Bump | 銅柱凸點 |
| Cu-Cu Hybrid Bonding | 銅-銅混合鍵合 |
| Current Density | 電流密度 |
| Current Leakage Test | 電流漏測 |
| Current Mirror | 電流鏡 |
| Current Sense | 電流偵測 |
| Dark Current | 暗電流 |
| Decoupling Capacitance Integration | 去耦電容整合 |
| Decoupling Capacitor | 去耦電容 |
| Deep Submicron Technology | 深次微米技術 |
| Deep Trench Isolation (DTI) | 深溝槽隔離 |
| Defect Density | 缺陷密度 |
| Defect Localization | 缺陷定位 |
| Dense Interconnect Technology | 高密度互連技術 |
| Deposition | 沉積 |
| Deprocessing | 去製程 |
| Design for Manufacturability (DFM) | 可製造性設計 |
| Design For Test (DFT) | 可測性設計 |
| Design Intent Verification | 設計意圖驗證 |
| Design of Experiment (DOE) | 實驗設計 |
| Design Rule Check (DRC) | 設計規則檢查 |
| Device Embedding | 裝置嵌入 |
| Device Matching | 裝置匹配 |
| Device Miniaturization | 裝置微型化 |
| Dicing | 切割 |
| Dicing Before Grinding (DBG) | 切割先行研磨技術 |
| Die | 晶粒 |
| Die Attach | 晶粒黏著 |
| Die Attach Epoxy | 晶粒黏合環氧膠 |
| Die Attach Film (DAF) | 晶粒貼合膜 |
| Die Attach Solder Paste | 晶粒黏合錫膏 |
| Die Edge Protection | 晶粒邊緣保護 |
| Die Edge Reinforcement | 晶粒邊緣加強 |
| Die Partitioning | 晶粒分區 |
| Die Shrink | 晶片縮小 |
| Die Shrinkage Compensation | 晶粒縮小補償 |
| Die Stacking | 晶粒堆疊 |
| Dielectric Anisotropy | 介電異向性 |
| Dielectric Breakdown | 介電擊穿 |
| Dielectric Breakdown Voltage | 介電擊穿電壓 |
| Dielectric Constant | 介電常數 |
| Dielectric Encapsulation | 介電包覆 |
| Dielectric Isolation | 介電隔離 |
| Dielectric Layer Formation | 介電層形成 |
| Dielectric Strength | 介電強度 |
| Die-to-Die Interconnect | 晶粒對晶粒互連 |
| Die-to-Die Power Delivery | 晶粒對晶粒電力傳輸 |
| Die-to-Substrate Bonding | 晶粒對基板鍵合 |
| Die-to-Wafer Bonding | 晶粒對晶圓鍵合 |
| Diffusion | 擴散 |
| Diffusion Barrier | 擴散阻障 |
| Diffusion Source | 擴散源 |
| Digital Core | 數位核心 |
| Digital Signal Conditioning | 數位信號調節 |
| Digital Signal Processing (DSP) | 數位信號處理 |
| Digital Twin | 數位雙胞胎 |
| Digital-to-Analog Converter (DAC) | 數位類比轉換器 |
| Digital-to-Time Converter (DTC) | 數位到時間轉換器 |
| Direct Bond Copper Interconnect | 直接鍵合銅互連 |
| Direct Bond Interconnect (DBI) | 直接鍵合互連 |
| Direct Current (DC) Power Integrity | 直流電源完整性 |
| Direct Die Attachment | 直接晶粒黏合 |
| Direct Wafer Bonding | 直接晶圓接合 |
| Doping | 摻雜 |
| Double-Sided Chip Mounting | 雙面晶片裝載 |
| Double-Sided RDL | 雙面重分佈層 |
| DRAM (Dynamic Random Access Memory) | 動態隨機存取記憶體 |
| Dry Etching | 乾式蝕刻 |
| Dual Damascene | 雙重大馬士革工藝 |
| Dual In-line Package (DIP) | 雙列直插封裝 |
| Dynamic Power | 動態功耗 |
| Dynamic Random Access Memory (DRAM) | 動態隨機存取記憶體 |
| EBL (Electron Beam Lithography) | 電子束微影 |
| EDA (Electronic Design Automation) | 電子設計自動化 |
| Edge Triggering | 邊緣觸發 |
| EEPROM (Electrically Erasable Programmable Read-Only Memory) | 電擦除可程式唯讀記憶體 |
| Electrical Conductive Adhesive (ECA) | 導電膠 |
| Electrical Crosstalk | 電串擾 |
| Electrical Die Sorting (EDS) | 電性晶粒分選 |
| Electrical Insulation | 電氣絕緣 |
| Electrical Overstress (EOS) | 電應力過載 |
| Electrical Overstress (EOS) Protection | 電應力過載保護 |
| Electrical Parameter Variation | 電參數變異 |
| Electrical Test | 電測試 |
| Electrical Test Yield | 電測良率 |
| Electrochemical Deposition (ECD) | 電化學沉積 |
| Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) | 無電鍍鎳鈀浸金 |
| Electroless Nickel Immersion Gold (ENIG) | 無電鍍鎳浸金 |
| Electroless Plating | 無電鍍 |
| Electromagnetic Compatibility (EMC) | 電磁相容性 |
| Electromagnetic Interference (EMI) Control | 電磁干擾控制 |
| Electromagnetic Shielding | 電磁屏蔽 |
| Electromigration | 電遷移 |
| Electron Beam Lithography (EBL) | 電子束微影 |
| Electron Mobility | 電子遷移率 |
| Electro-Optical Interconnect | 電光互連 |
| Electroplated Copper Pillars | 電鍍銅柱 |
| Electrostatic Actuator | 靜電致動器 |
| Electrostatic Discharge Sensitivity (ESDS) | 靜電敏感性 |
| Electro-Thermal Modeling | 電熱模型 |
| Electro-Thermal Simulation | 電熱模擬 |
| Embedded Active Device | 嵌入式有源器件 |
| Embedded Component Package | 嵌入式元件封裝 |
| Embedded Die | 嵌入式晶片 |
| Embedded Dielectric Shielding | 嵌入式介電屏蔽 |
| Embedded Heat Spreader | 嵌入式散熱器 |
| Embedded Memory | 嵌入式記憶體 |
| Embedded Multi-Die Interconnect Bridge (EMIB) | 嵌入式多晶片互連橋 |
| Embedded Passives | 嵌入式被動元件 |
| Embedded RF Front-End | 嵌入式射頻前端 |
| Embedded Sensor Integration | 嵌入式感測器整合 |
| Embedded Trace Substrate (ETS) | 嵌入式線路基板 |
| Embedded Wafer-Level Ball Grid Array (eWLB) | 嵌入式晶圓級球柵陣列 |
| Embedded Wafer-Level Package (eWLP) | 嵌入式晶圓級封裝 |
| EMI Shielding for RF Packaging | 射頻封裝的電磁屏蔽 |
| EMI Suppression Layer | 電磁干擾抑制層 |
| Enhanced Heat Dissipation | 增強散熱 |
| Enhanced Mold Compound | 加強型模塑材料 |
| Enhanced Substrate Rigidity | 增強基板剛性 |
| Environmental Stress Test | 環境應力測試 |
| Epitaxial Wafer | 外延晶圓 |
| Epitaxy | 外延 |
| Epoxy Adhesive | 環氧黏著劑 |
| Epoxy Molding Compound (EMC) | 環氧模塑料 |
| ESD (Electrostatic Discharge) | 靜電放電 |
| Etching | 蝕刻 |
| Eutectic Bonding | 共晶鍵合 |
| Extreme Ultraviolet (EUV) | 極紫外光 |
| Fabrication | 製造 |
| Fabrication Yield | 製造良率 |
| Failure Analysis (FA) | 失效分析 |
| Failure Mechanism | 失效機制 |
| Failure-In-Time (FIT) | 失效時間 |
| Fan-In Package | 扇入封裝 |
| Fan-In Wafer-Level Packaging (FI-WLP) | 晶圓級扇入封裝 |
| Fan-Out Die Placement | 扇出晶粒放置 |
| Fan-Out Package | 扇出封裝 |
| Fan-Out Panel-Level Packaging (FO-PLP) | 面板級扇出型封裝 |
| Fan-Out Through Mold Via (TMV) | 扇出型穿模導孔封裝 |
| Fan-Out Through Silicon Via | 扇出型矽穿孔封裝 |
| Fan-Out Wafer-Level Packaging (FO-WLP) | 晶圓級扇出封裝 |
| Fan-Out Wafer-on-Wafer (FoW2W) | 扇出晶圓對晶圓封裝 |
| Fault Isolation | 故障隔離 |
| Field Isolation | 場隔離 |
| Field Oxide | 場氧化層 |
| Field Programmable Gate Array (FPGA) | 現場可程式邏輯閘陣列 |
| Fin Patterning | 鰭式圖形化 |
| Fine Pitch Flip Chip | 細間距覆晶 |
| Fine-Line Patterning | 細線圖案製作 |
| Fine-Line Substrate | 細線基板 |
| Fine-Pitch Copper Pillars | 細間距銅柱 |
| Fine-Pitch Die Bonding | 細間距晶粒黏合 |
| Fine-Pitch Interconnect | 細間距互連 |
| Fine-Pitch Package Design | 細間距封裝設計 |
| Fine-Pitch RDL | 細間距重分佈層 |
| Fine-Pitch Solder Bumping | 細間距錫凸點 |
| FinFET | 鰭式場效電晶體 |
| Flexible Interposer | 彈性中介層 |
| Flip Chip | 覆晶封裝 |
| Flip Chip Ball Grid Array (FCBGA) | 覆晶球柵陣列封裝 |
| Flip Chip Interconnect | 翻晶互連 |
| Flip Chip on Substrate | 覆晶基板封裝 |
| Flip-Chip Ball Grid Array (FCBGA) | 翻晶球柵陣列封裝 |
| Flip-Chip on Leadframe (FCOL) | 覆晶引線框封裝 |
| Flip-Chip Package | 覆晶封裝 |
| Flip-Chip Wafer-Level Package (FCWLP) | 覆晶晶圓級封裝 |
| Floating Gate | 浮動閘極 |
| Foundry | 晶圓代工廠 |
| FPGA (Field Programmable Gate Array) | 現場可程式邏輯閘陣列 |
| Frequency Divider | 頻率分頻器 |
| Frequency Response | 頻率響應 |
| Frequency-Selective Surface (FSS) Design | 頻率選擇性表面設計 |
| Frontend of Line (FEOL) | 前段製程 |
| Frontend Process | 前端製程 |
| Front-Side Metallization | 前側金屬化 |
| Functional Block Diagram | 功能方塊圖 |
| Functional Test | 功能測試 |
| Functional Verification | 功能驗證 |
| Functional Yield | 功能性良率 |
| GaN (Gallium Nitride) | 氮化鎵 |
| Gate Electrode | 閘極電極 |
| Gate Length | 閘極長度 |
| Gate Oxide | 閘極氧化層 |
| Gate Resistance | 閘極電阻 |
| Gate Width | 閘極寬度 |
| Gate-All-Around (GAA) FET | 全包覆閘極場效電晶體 |
| Germanium | 鍺 |
| Glass Core Substrate | 玻璃芯基板 |
| Glass Substrate | 玻璃基板 |
| Hall Effect Sensor | 霍爾效應感測器 |
| Hard Mask | 硬光罩 |
| Heat Dissipation Layer | 散熱層 |
| Heat Dissipation Path | 散熱路徑 |
| Heat Sink | 散熱片 |
| Heat Spreaders | 散熱器 |
| Heat Spreading Layer | 散熱層 |
| Hermetic Sealing | 氣密封裝 |
| Hermetically Sealed Cavity | 氣密封裝腔體 |
| Heterogeneous Integration | 異質整合 |
| Heterogeneous Packaging | 異質封裝 |
| High Aspect Ratio Etching | 高縱橫比蝕刻 |
| High Aspect Ratio Interconnect | 高縱橫比互連 |
| High Aspect Ratio Through Silicon Via | 高縱橫比矽穿孔 |
| High Aspect Ratio TSV | 高縱橫比矽穿孔 |
| High Bandwidth Interconnect | 高頻寬互連 |
| High Bandwidth Low Power Design | 高頻寬低功耗設計 |
| High Bandwidth Memory (HBM) | 高頻寬記憶體 |
| High Density Interconnect (HDI) | 高密度互連 |
| High Dielectric Breakdown Material | 高介電擊穿材料 |
| High Dielectric Strength Material | 高介電強度材料 |
| High Frequency (HF) Testing | 高頻測試 |
| High Modulus Encapsulation | 高模量封裝 |
| High Power Density Application | 高功率密度應用 |
| High Power Density Packaging | 高功率密度封裝 |
| High Thermal Conductivity Material | 高熱導材料 |
| High Thermal Conductivity Substrate | 高熱導基板 |
| High Voltage Device | 高電壓裝置 |
| High Voltage Packaging | 高電壓封裝 |
| High Voltage Tolerance | 高電壓容忍度 |
| High-Aspect-Ratio Trench | 高縱橫比槽 |
| High-Density Bump Technology | 高密度凸點技術 |
| High-Density Interconnect (HDI) | 高密度互連 |
| High-Density RDL | 高密度重分佈層 |
| High-Density Signal Routing | 高密度信號路由 |
| High-Frequency Dielectric Layer | 高頻介電層 |
| High-Frequency Electromagnetic Interference | 高頻電磁干擾 |
| High-Frequency PCB | 高頻印刷電路板 |
| High-Frequency Signal Isolation | 高頻信號隔離 |
| High-K Dielectrics | 高介電材料 |
| High-K Metal Gate (HKMG) | 高介電金屬閘極 |
| High-Performance Computing Package (HPC) | 高效能運算封裝 |
| High-Precision Dicing | 高精度切割 |
| High-Speed Serial Interface | 高速串行接口 |
| High-Voltage Breakdown | 高電壓擊穿 |
| Hole Mobility | 空穴遷移率 |
| Hot Carrier Effect | 熱載流子效應 |
| Hot Carrier Injection (HCI) | 熱載流子注入 |
| Hot Carrier Reliability | 熱載流子可靠性 |
| Hot Melt Underfill | 熱熔填充膠 |
| HVIC (High Voltage Integrated Circuit) | 高壓集成電路 |
| Hybrid Bonding | 混合鍵合 |
| Hybrid Package Assembly | 混合封裝組裝 |
| Hybrid Wafer Bonding | 混合晶圓鍵合 |
| In-Package Decoupling | 封裝內去耦 |
| Input Capacitance | 輸入電容 |
| Input/Output (I/O) Buffer | 輸入/輸出緩衝器 |
| Insulated Gate Bipolar Transistor (IGBT) | 絕緣閘雙極型電晶體 |
| Integrated Circuit (IC) | 集成電路 |
| Integrated Circuit Layout | 集成電路佈局 |
| Integrated Fan-Out (InFO) | 集成扇出封裝 |
| Integrated Heat Spreader (IHS) | 整合散熱器 |
| Integrated Inductor | 集成電感 |
| Integrated Voltage Regulator (IVR) | 集成式電壓調節器 |
| Integrated Voltage Regulator (IVR) | 集成電壓調節器 |
| Interconnect Density | 互連密度 |
| Interlayer Dielectric (ILD) | 層間介電層 |
| Intermetal Dielectric (IMD) | 金屬間介電層 |
| Interposer | 中介層 |
| Ion Beam Etching | 離子束蝕刻 |
| Ion Implantation | 離子佈植 |
| Isolation Process | 隔離製程 |
| Junction Temperature | 結溫 |
| Laser Dicing | 雷射切割 |
| Laser Drilling for Microvias | 微孔雷射鑽孔 |
| Laser Scribing | 雷射劃線 |
| Laser-Assisted Bonding | 雷射輔助鍵合 |
| Laser-Assisted Direct Copper Bonding | 雷射輔助直接銅鍵合 |
| Latch-Up | 鎖定效應 |
| Layered Package Structure | 層狀封裝結構 |
| Layer-to-Layer Crosstalk | 層間串擾 |
| Leadframe Package | 引線框封裝 |
| Lead-Free Solder | 無鉛焊料 |
| Lead-Free Underfill | 無鉛填充膠 |
| Leakage Current | 漏電流 |
| Leakage Current Suppression | 漏電流抑制 |
| Leakage Power | 漏電功耗 |
| Light Emitting Diode (LED) | 發光二極體 |
| Linewidth | 線寬 |
| Lithographic Resolution | 微影解析度 |
| Lithography | 光刻 |
| Load Balancing | 負載平衡 |
| Load Pull Test | 負載拉伸測試 |
| Logic Analyzer | 邏輯分析儀 |
| Logic Device | 邏輯裝置 |
| Logic Gate | 邏輯閘 |
| Logic Simulation | 邏輯模擬 |
| Long-Term Reliability | 長期可靠性 |
| Long-Term Thermal Stability | 長期熱穩定性 |
| Low Dielectric Constant Material | 低介電常數材料 |
| Low Dropout Regulator (LDO) | 低壓降穩壓器 |
| Low K Dielectrics | 低K介電材料 |
| Low Noise Amplifier (LNA) | 低噪音放大器 |
| Low Power Consumption Bonding | 低功耗鍵合 |
| Low Power Design | 低功耗設計 |
| Low Profile Die | 低剖面晶粒 |
| Low Profile Package | 低剖面封裝 |
| Low Resistance Path | 低阻抗通路 |
| Low Resistance Path (LRP) | 低阻抗路徑 |
| Low Temperature Solder | 低溫錫焊 |
| Low Warpage Mold Compound | 低翹曲模塑材料 |
| Low-K Dielectric | 低介電常數材料 |
| Low-K Dielectrics | 低介電材料 |
| Low-Loss Dielectric Material | 低損耗介電材料 |
| Low-Power Wideband Interface | 低功耗寬頻接口 |
| Low-Temperature Bonding | 低溫鍵合 |
| Low-Temperature Wafer Bonding | 低溫晶圓鍵合 |
| Mask Alignment | 光罩對準 |
| Mechanical Bump Reliability | 機械凸點可靠性 |
| Mechanical Robustness | 機械穩固性 |
| Mechanical Shock Resistance | 機械衝擊耐受性 |
| Memory Cell | 記憶體單元 |
| Memory Controller | 記憶體控制器 |
| Memory-on-Logic (MoL) Integration | 記憶體對邏輯整合 |
| MEMS (Micro-Electro-Mechanical Systems) | 微機電系統 |
| Metal Interconnect | 金屬互連 |
| Metal Layer | 金屬層 |
| Metal Stack | 金屬堆疊 |
| Metal-Insulator-Metal (MIM) | 金屬-絕緣體-金屬結構 |
| Metallization Process | 金屬化製程 |
| Micro Bump | 微凸點 |
| Micro Leadframe | 微引線框 |
| Microbump | 微凸點 |
| Microcontroller Unit (MCU) | 微控制單元 |
| Micro-Electro-Mechanical System (MEMS) | 微機電系統 |
| Microfabrication | 微細加工 |
| Micro-Through Via | 微導通孔 |
| Micro-Transfer Printing | 微轉印技術 |
| Microvia | 微通孔 |
| Moisture Sensitivity Level (MSL) | 濕度敏感性等級 |
| Mold Compound | 封裝材料 |
| Molded Interconnect Substrate (MIS) | 模製互連基板 |
| Molded Underfill | 模塑填充膠 |
| Monolithic Integration | 單片集成 |
| Monolithic Microwave Integrated Circuit (MMIC) | 單片微波集成電路 |
| MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) | 金氧半場效電晶體 |
| Multi-Chip Interconnection | 多晶片互連 |
| Multi-Chip Module (MCM) | 多晶片模組 |
| Multi-Chip Module Package | 多晶片模組封裝 |
| Multi-Chip Package (MCP) | 多晶片封裝 |
| Multi-Die Integration | 多晶片整合 |
| Multi-Die Package Integration | 多晶粒封裝整合 |
| Multi-Functional Fan-Out | 多功能扇出封裝 |
| Multi-Functional Package | 多功能封裝 |
| Multi-Gate Transistor | 多閘場效電晶體 |
| Multi-Layer Fan-Out (MLFO) | 多層扇出封裝 |
| Multi-Layer Substrate with RDL | 帶重分佈層的多層基板 |
| Multi-Level Interconnect | 多層互連 |
| Multi-Stacked Substrate | 多層堆疊基板 |
| NAND Flash | NAND快閃記憶體 |
| Nano-Coated TSVs | 奈米塗層矽穿孔 |
| Nano-Coating for Corrosion Resistance | 奈米塗層防腐蝕 |
| Nano-Electromechanical Systems (NEMS) | 奈米機電系統 |
| Nanoimprint Lithography | 奈米壓印光刻 |
| Nano-Patterned RDL | 奈米圖案重分佈層 |
| Negative Bias Temperature Instability (NBTI) | 負偏壓溫度不穩定性 |
| Negative Channel Metal Oxide Semiconductor (NMOS) | 負溝道金氧半導體 |
| Negative Feedback | 負回饋 |
| Noise Margin | 雜訊容限 |
| Noise Suppression | 噪音抑制 |
| Non-Volatile Memory | 非揮發性記憶體 |
| NOR Flash | NOR快閃記憶體 |
| On-Chip ESD Protection | 晶片上的靜電保護 |
| On-Chip Oscillator | 晶片內振盪器 |
| Organic LED (OLED) | 有機發光二極體 |
| Organic Mold Compound | 有機模塑材料 |
| Organic Substrate | 有機基板 |
| Oscillator Stability | 振盪器穩定性 |
| Out-of-Plane Conductivity | 平面外導電性 |
| Overcurrent Protection (OCP) | 過電流保護 |
| Over-Voltage Protection (OVP) | 過壓保護 |
| Oxidation | 氧化 |
| Oxide Reliability | 氧化層可靠性 |
| Package Body Size Shrinkage | 封裝體積縮小 |
| Package Delamination | 封裝剝離 |
| Package Inductive Coupling | 封裝感應耦合 |
| Package Integration | 封裝整合 |
| Package Noise Mitigation | 封裝噪聲抑制 |
| Package Stacking | 封裝堆疊 |
| Package Warpage | 封裝翹曲 |
| Package Warpage Control | 封裝翹曲控制 |
| Package-on-Package (PoP) | 封裝對封裝 |
| Package-on-Package Stacking | 封裝疊層封裝 |
| Packaging | 封裝 |
| Pad Cratering | 焊盤破裂 |
| Panel Level Packaging (PLP) | 面板級封裝 |
| Parametric Testing | 參數測試 |
| Parametric Yield | 參數良率 |
| Passivation | 鈍化 |
| Passivation Coating | 鈍化塗層 |
| Passivation Layer | 鈍化層 |
| Passive Component Integration | 被動元件整合 |
| Passive Device | 被動裝置 |
| Passive Interposer | 被動中介層 |
| Phase-Locked Loop (PLL) | 鎖相環 |
| Photolithography | 光學微影 |
| Photolithography | 光刻技術 |
| Photomask | 光罩 |
| Physical Vapor Deposition (PVD) | 物理氣相沉積 |
| Plasma Etching | 電漿蝕刻 |
| Plasma Etching | 電漿蝕刻 |
| Plasma-Enhanced CVD (PECVD) | 電漿增強化學氣相沉積 |
| Plasma-Enhanced Etching (PEE) | 電漿增強蝕刻 |
| Plated Copper Through-Hole | 電鍍銅通孔 |
| Plating Process Control | 電鍍工藝控制 |
| Polymer RDL | 聚合物重分佈層 |
| Poly-Silicon | 多晶矽 |
| Positive Bias Temperature Instability (PBTI) | 正偏壓溫度不穩定性 |
| Power Amplifier (PA) | 功率放大器 |
| Power Amplifier Module | 功率放大模組 |
| Power Delivery Network (PDN) | 電源供應網路 |
| Power Density | 功率密度 |
| Power Dissipation | 功率耗散 |
| Power Dissipation Control | 功率耗散控制 |
| Power Integrity (PI) | 功率完整性 |
| Power Integrity Simulation | 電源完整性模擬 |
| Power MOSFET | 功率金氧半場效電晶體 |
| Power Sequencing | 電源排序 |
| Power System on Chip (Power SoC) | 電源系統晶片 |
| Power-Aware Signal Integrity | 考慮功耗的信號完整性 |
| Power-On Reset (POR) | 上電重置 |
| Power-Up Sequence | 上電序列 |
| Precision Dicing | 精密切割 |
| Precision Thermal Expansion Control | 精密熱膨脹控制 |
| Printed Circuit Heat Exchanger (PCHE) | 印刷電路板熱交換器 |
| Probe Card | 探針卡 |
| Probe Test | 探針測試 |
| Probing Yield | 探針測試良率 |
| Process Control Monitoring (PCM) | 製程控制監控 |
| Process Development Kit (PDK) | 製程開發套件 |
| Process Drift | 製程偏移 |
| Process Flow | 製程流程 |
| Process Integration | 製程整合 |
| Process Node | 製程節點 |
| Process Qualification | 製程認證 |
| Process Robustness | 製程穩健性 |
| Process Variation | 製程變異 |
| Process Window | 製程窗口 |
| Process-Induced Stress Management | 製程誘發應力管理 |
| Programmable Logic Device (PLD) | 可程式邏輯裝置 |
| Pseudo-Random Binary Sequence (PRBS) | 偽隨機二進位序列 |
| Quad Flat Package (QFP) | 四方扁平封裝 |
| Quality Control (QC) | 品質控制 |
| Quantum Dot | 量子點 |
| Radio Frequency (RF) | 射頻 |
| Radio Frequency (RF) Passive Integration | 射頻被動元件整合 |
| Radio Frequency Interference (RFI) | 射頻干擾 |
| Rapid Thermal Processing (RTP) | 快速熱處理 |
| Real-Time Temperature Sensing | 即時溫度感測 |
| Recessed Channel | 凹陷通道 |
| Reconstituted Panel-Level Processing | 重組面板級處理 |
| Reconstituted Wafer Processing | 重組晶圓處理 |
| Redistribution Layer (RDL) | 重分佈層 |
| Redistribution Layer (RDL) Stack | 重分佈層堆疊 |
| Redistribution Layer Design | 重分佈層設計 |
| Redistribution Layer Inspection | 重分佈層檢測 |
| Redistribution Layer Thinning | 重分佈層薄化 |
| Redundant Power | 冗餘電源 |
| Reflow Process | 重流焊接工藝 |
| Reflow Soldering | 回焊 |
| Reflow-Enhanced Flip Chip | 重流焊增強覆晶封裝 |
| Reliability | 可靠性 |
| Reliability Growth Testing | 可靠性增長測試 |
| Reliability Qualification | 可靠性認證 |
| Reliability Test | 可靠性測試 |
| Resist Stripping | 光阻剝離 |
| Resistor Network | 電阻網絡 |
| Resonance Frequency | 共振頻率 |
| RF Front-End Module | 射頻前端模組 |
| RF Shielding for Interconnects | 互連射頻屏蔽 |
| RF Switch | 射頻開關 |
| Root Cause Analysis | 根本原因分析 |
| Scribe Line | 劃線區 |
| Self Heating | 自加熱 |
| Self-Aligned Contact (SAC) | 自對準接觸 |
| Self-Aligned Via | 自對準導通孔 |
| Self-Alignment | 自對準 |
| Semiconductor | 半導體 |
| Semiconductor Grade | 半導體級別 |
| Semiconductor Laser | 半導體雷射 |
| Sequential Die Attach | 順序晶粒黏合 |
| Sequential Wafer Bonding | 順序晶圓鍵合 |
| Shallow Trench Isolation (STI) | 淺溝槽隔離 |
| Sheet Resistance | 片電阻 |
| Short-Circuit Protection | 短路保護 |
| SiC (Silicon Carbide) | 碳化矽 |
| Sidewall Protection | 側壁保護 |
| Sidewall Redistribution Layer | 側壁重分佈層 |
| Signal Amplification | 信號放大 |
| Signal Conditioning | 信號調節 |
| Signal Degradation Analysis | 信號衰減分析 |
| Signal Integrity (SI) | 信號完整性 |
| Signal Tracing in RDL | 重分佈層信號追蹤 |
| Signal-to-Noise Ratio (SNR) | 信噪比 |
| Silicon | 矽 |
| Silicon Carbide (SiC) | 碳化矽 |
| Silicon Interposer | 矽中介層 |
| Silicon Photonics | 矽光子 |
| Single Event Latch-up (SEL) | 單一事件鎖定 |
| Single Event Upset (SEU) | 單一事件擾動 |
| Single Photon Avalanche Diode (SPAD) | 單光子雪崩二極體 |
| SiP Assembly | 系統級封裝組裝 |
| Small Outline Package (SOP) | 小型輪廓封裝 |
| SoC (System on Chip) | 系統單晶片 |
| Solder Ball | 錫球 |
| Solder Jet Bumping | 錫焊噴射凸點 |
| Solder Resist Coating | 錫焊防焊塗層 |
| Spin Coating | 旋轉塗佈 |
| Sputtering | 濺鍍 |
| SRAM (Static Random Access Memory) | 靜態隨機存取記憶體 |
| SRAM Cell | 靜態記憶體單元 |
| Stacked Die | 疊層晶片 |
| Stacked Memory Integration | 疊層記憶體整合 |
| Stacked TSV | 疊層矽穿孔 |
| Stack-Up Design for Reliability | 可靠性堆疊設計 |
| Static Power | 靜態功耗 |
| Static Random Access Memory (SRAM) | 靜態隨機存取記憶體 |
| Strain-Relief Packaging | 應變釋放封裝 |
| Stress Buffer Layer | 應力緩衝層 |
| Stress Compensating Encapsulation | 應力補償封裝 |
| Stress Compensating Layer | 應力補償層 |
| Stress Minimization Design | 應力最小化設計 |
| Stress Relief Buffer | 應力釋放緩衝層 |
| Stress Relief Solder Joint | 應力釋放焊接點 |
| Stress Test | 應力測試 |
| Stress-Induced Leakage Current (SILC) | 應力引發漏電流 |
| Substrate | 基板 |
| Substrate Embedded Passive Component | 基板嵌入被動元件 |
| Substrate Heating | 基板加熱 |
| Substrate Integrated Passive Components | 基板嵌入被動元件 |
| Substrate Interposer | 基板中介層 |
| Substrate-Free Package | 無基板封裝 |
| Substrate-Like PCB (SLP) | 類基板印刷電路板 |
| Supply Voltage | 供應電壓 |
| Surface Mount Technology (SMT) | 表面貼裝技術 |
| Surface Reconstruction | 表面重建 |
| Switching Speed | 切換速度 |
| System Level Test (SLT) | 系統層級測試 |
| System-Level ESD Protection | 系統級靜電放電保護 |
| System-Level Packaging | 系統層級封裝 |
| System-Level Testing | 系統級測試 |
| System-on-a-Chip (SoC) | 系統單晶片 |
| Technology Computer-Aided Design (TCAD) | 技術輔助設計 |
| Temperature Cycle Test | 溫度循環測試 |
| Temperature Gradient Tolerance | 溫度梯度容忍度 |
| Test Coverage | 測試覆蓋率 |
| Test Data Compression | 測試數據壓縮 |
| Test Fixture | 測試夾具 |
| Testing | 測試 |
| Thermal Compression Bonding (TCB) | 熱壓鍵合 |
| Thermal Conductive Adhesive | 熱導黏著劑 |
| Thermal Conductive Interface Material (TCIM) | 熱導介面材料 |
| Thermal Conductivity | 熱導率 |
| Thermal Cycling Reliability | 熱循環可靠性 |
| Thermal Cycling Test | 熱循環測試 |
| Thermal Gradient | 熱梯度 |
| Thermal Interface Management | 熱界面管理 |
| Thermal Interface Material (TIM) | 熱界面材料 |
| Thermal Management | 熱管理 |
| Thermal Management Unit (TMU) | 熱管理單元 |
| Thermal Oxidation | 熱氧化 |
| Thermal Oxide | 熱氧化層 |
| Thermal Resistance | 熱阻 |
| Thermal Resistance Measurement | 熱阻測量 |
| Thermal Runaway | 熱失控 |
| Thermal Shock Test | 熱衝擊測試 |
| Thermal Shutdown | 熱關閉 |
| Thermal Spread | 熱擴散 |
| Thermally Enhanced Mold Compound | 增強型模塑材料 |
| Thermo-Compression Bonded RDL | 熱壓鍵合重分佈層 |
| Thermocompression Bonding | 熱壓鍵合 |
| Thermocompression Flip Chip Bonding | 熱壓覆晶鍵合 |
| Thermo-Mechanical Modeling | 熱機械模型 |
| Thermo-Mechanical Simulation | 熱機械模擬 |
| Thermoplastic Encapsulation | 熱塑性封裝 |
| Thermosonic Bonding | 熱超音波鍵合 |
| Thin Die Stacking | 薄晶粒堆疊 |
| Thin Film | 薄膜 |
| Thin Film Deposition | 薄膜沉積 |
| Thin Wafer Handling | 薄晶圓處理 |
| Thin-Film Encapsulation | 薄膜封裝 |
| Thin-Wafer Bonding | 薄晶圓鍵合 |
| Threshold Voltage | 臨界電壓 |
| Through Glass Via (TGV) | 穿玻璃孔 |
| Through-Metal Via (TMV) | 穿金屬孔 |
| Through-Mold Via (TMV) | 穿模導通孔 |
| Through-Mold Via Fan-Out | 扇出型穿模導通孔封裝 |
| Through-Silicon Via (TSV) | 矽穿孔技術 |
| Through-Substrate Via (TSV) | 穿基板導孔 |
| Through-Wafer Interconnect | 穿晶圓互連 |
| Time-to-Digital Converter (TDC) | 時間數位轉換器 |
| Total Ionizing Dose (TID) | 總電離劑量 |
| Transistor-Transistor Logic (TTL) | 電晶體-電晶體邏輯 |
| Transmission Gate | 傳輸閘 |
| Transmission Line Model | 傳輸線模型 |
| TSV (Through-Silicon Via) | 矽穿孔技術 |
| TSV with High Aspect Ratio | 高縱橫比矽穿孔 |
| Ultra-Fine Bump | 超細凸點 |
| Ultra-Fine Line RDL | 超細線重分佈層 |
| Ultra-Thin Body and Box (UTBB) | 超薄體與框體 |
| Ultra-Thin Package | 超薄封裝 |
| Ultra-Thin Wafer Handling | 超薄晶圓處理 |
| Under Bump Metallurgy (UBM) | 凸點下金屬化 |
| Under-Bump Metallization (UBM) | 凸點下金屬化 |
| Underfill | 填充膠 |
| Underfill Void Detection | 填充物氣泡檢測 |
| Underlayer Metallization | 下層金屬化 |
| UV Exposure | 紫外光曝光 |
| Variable Gain Amplifier (VGA) | 可變增益放大器 |
| Vertical Integration | 垂直整合 |
| Vertical Interconnect Access (VIA) | 垂直互連通孔 |
| Vertical Scaling | 垂直縮放 |
| Void-Free Encapsulation | 無空洞包覆 |
| Void-Free Solder Technology | 無氣孔焊接技術 |
| Void-Free Underfill | 無氣孔填充膠 |
| Voltage Drop | 電壓降 |
| Voltage Drop Compensation (VDC) | 電壓降補償 |
| Voltage Drop Test | 電壓降測試 |
| Voltage Regulator Module (VRM) | 電壓調整模組 |
| Voltage-Controlled Oscillator (VCO) | 電壓控制振盪器 |
| Wafer | 晶圓 |
| Wafer Alignment | 晶圓對準 |
| Wafer Back Grinding | 晶圓背研 |
| Wafer Bonding | 晶圓鍵合 |
| Wafer Bonding Alignment | 晶圓鍵合對準 |
| Wafer Bonding with Adhesive Layer | 帶黏著層的晶圓鍵合 |
| Wafer De-Bonding | 晶圓去鍵合 |
| Wafer Encapsulation | 晶圓封裝 |
| Wafer Handling Automation | 晶圓處理自動化 |
| Wafer Level Packaging (WLP) | 晶圓級封裝 |
| Wafer Level Reliability (WLR) | 晶圓級可靠性 |
| Wafer Reconstitution | 晶圓重組 |
| Wafer Sort | 晶圓測試 |
| Wafer Thinning | 晶圓減薄 |
| Wafer Thinning Process | 晶圓減薄工藝 |
| Wafer Transfer | 晶圓轉移 |
| Wafer-Level Chip Scale Package (WLCSP) | 晶圓級晶片尺寸封裝 |
| Wafer-Level Packaging (WLP) | 晶圓級封裝 |
| Wafer-to-Wafer Bonding | 晶圓對晶圓鍵合 |
| Wafer-to-Wafer Stacking | 晶圓對晶圓堆疊 |
| Warpage Control | 翹曲控制 |
| Wet Etching | 濕式蝕刻 |
| Wire Bond Encapsulation | 金線鍵合封裝 |
| Wire Bonding | 線接合 |
| Wire Sweep | 線移動 |
| X-Ray Inspection | X光檢測 |
| Yield | 良率 |
| Yield Enhancement | 良率提升 |
